1. Field of the Invention
The present invention relates to an integrated circuit designing support apparatus and a method for the same.
2. Description of the Related Art
Rapid increase of personal computers and cellular phones leads increase of demand of semiconductor devices, together with higher reliability of the semiconductor device. A defect in an operation circuit such as ALU (Arithmetic and Logical Unit) is important since it causes a fatal problem in the semiconductor device.
Recently, design and manufacturing technique of a semiconductor device, especially LSI (Large-Scale Integrated circuit), has been remarkably and rapidly advanced. In a design stage of LSI, duplication of a circuit portion is carried out to produce a dual circuit of a first circuit and a second circuit so as to improve the reliability of the device. For example, in Japanese Laid Open Patent Application (JP-A-Heisei 11-102386), outputs of the first circuit and outputs of the second circuit are compared, and the design is changed when a difference is detected between the outputs
Such a method of duplicating the circuit portion is effective to improve the reliability of LSI. In this method, there is a case that the first circuit and the second circuit are integrated into one circuit in a process of a logical synthesis in the design stage. The logic of the second circuit is basically same as that of the first circuit. For this reason, the first circuit and the second circuit are integrated erroneously when the circuit is optimized in the process of the logical synthesis in the design stage. FIG. 1 shows a state that the first circuit and the second circuit are integrated.
In conjunction with the above description, an integrated circuit designing apparatus is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 9-204460). In this conventional example, the integrated circuit designing support apparatus is used to support the designing of an integrated circuit by using a hardware description language. First and second circuit design data are divided in units of modules to generate a plurality of first and second module design data. Specified one or more of the plurality of first and second module design data are extracted and the extracted first and second module design data are compared with each other between corresponding modules to check whether the corresponding modules are logically same. In the other modules, it is checked whether cells and signal lines are completely same between the modules.